Research

Chip Architecture

A Chiplet Expert-Reuse Architecture for MoE Inference

Mixture-of-experts models expand parameter capacity through sparse activation, but Top-k routing creates expert hotspots, random weight loading, inter-chiplet scatter-gather traffic, and synchronization tail latency in chiplet systems.

Inference Systems

A Lifecycle-Aware KV Cache System for Agent Inference

Agent inference extends a single model call into a long-lived workflow of planning, tool execution, observation integration, validation, and retries, turning the KV cache from a temporary per-request tensor into execution state spanning multiple turns.

Quantization & Compilation

Compiler Optimization for Large Models on Edge NPUs

Edge neural processing units offer energy-efficient matrix arrays, tightly coupled on-chip memory, and asynchronous DMA. However, static graphs, limited dynamic shapes, restricted address spaces, and power and thermal constraints conflict structurally with autoregressive state, variable sequences, and mixed operators in large models.

Quantization & Compilation

Portable FP4 Quantization for Heterogeneous Accelerators

FP4 computing for large models is developing into a hardware ecosystem where MXFP4, NVFP4, and vendor-specific variants coexist.

Chip Architecture

The Evolution of Memory-Centric Architectures for Large-Model Inference

As reasoning models, long contexts, and agent applications evolve, the main inference bottleneck is shifting from insufficient peak compute to frequent movement of model weights, KV caches, expert parameters, and intermediate state across memory hierarchies and interconnects.

Research notes